The present invention relates to a data processing apparatus for executing the arithmetic processing of data in which the bit width of one word is not standard 2n bits.
Some of apparatuses for outputting or processing images, voices etc. employ data in which the bit width of one word is not standard 2n bits, in order to enhance the qualities of the images and the voices or to affix additional information to the images and voices. Such apparatuses include, for example, a so-called “third-generation portable telephone”, and an information processing apparatus which generates image data having a plurality of gradations. A digital signal processor (hereinbelow, termed “DSP”) or any other data processing apparatus is installed in such an apparatus, whereby various items of arithmetic processing are executed by converting the bit width of one word into standard 2n bits.
Now, a presented data processing apparatus will be described by taking as an example the DSP which is installed in the third-generation portable telephone.
Using the DSP, the third-generation portable telephone extracts the signals of several specified bandwidths from within a broad frequency bandwidth in order to favorably communicate at all times. Besides, from among the specified bandwidths, one of high reception sensitivity is especially selected for the communications. Incidentally, on this occasion, the DSP usually extracts the signals of the specified bandwidths by employing a technique called “digital matched filter (hereinbelow, termed “DMF”) algorithm”, but the technique itself is not pertinent to the subject matter of the present invention and shall be omitted from detailed description here.
In the presented data processing apparatus, data of 16 bits are outputted from a memory to an ALU atone time. However, data for use in arithmetic processing correspond only to 10 of the 16 bits. Therefore, the presented data processing apparatus wastefully outputs the data of 6 bits to the ALU at one time.
Moreover, the ALU has a built-in arithmetic unit of 32-bit width, but it uses only 10 bits in the 32-bit width. Therefore, the presented data processing apparatus wastes the arithmetic unit in correspondence with a 22-bit width.
With the intention of solving the drawbacks, there has been proposed a technique wherein the width of a bus is doubled (to 32 bits) so as to output data of 32 bits from the memory to the ALU, and the arithmetic unit is divided into higher-order 16 bits and lower-order 16 bits so as to arithmetically process the data in parallel. Even with this technique, however, the memory is used in correspondence with only 10 bits in spite of the 16-bit width thereof. Therefore, the presented data processing apparatus wastes 6 bits in the use of the memory.
In this manner, in the case where the arithmetic processing is done using the data of which one word does not have the standard bit width, the presented data processing apparatus has the problem that, since a reserved part (free area) is arranged between I-part data and R-part data, the built-in arithmetic unit of the ALU and the memory are wastefully used, so the processability of the arithmetic unit and the capacity of the memory cannot be effectively utilized.